1. Field of the Invention
The present invention generally relates to a chip fabrication procedure and, more particularly, to a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing, in which the chip is produced after a simulation on design validity and product performance is carried out so as to confirm the product advantage, such that the time requited for product testing is reduced and so is the fabrication cost.
2. Description of the Prior Art
In recent years, with the high development in electronic- and information-related industries, people have increasing needs for better performance of various electronic and information products. In view of this, the industries have made lots of efforts to develop various new products. These new products may, however, cooperate with different specifications from the conventional ones. It is inevitable that the new products with various specifications must be tested before they can be presented to the public. Therefore, product testing has become an important issue for the manufacturers.
For some chip design houses and chip manufacturers, the conventional procedure including steps from design to testing is as shown in FIG. 1. First of all, a chip design is provided (step 101). Secondly, simulation is performed on the chip design so as to test if the design responds correctly with respect to various testing commands (step 103). The procedure then proceeds with production of chips (step 105). Next, a motherboard corresponding to the designed chip is prepared (step 107). Later, a computer comprising the chip is assembled (step 109). An operating system (OS) as well as software for performance testing is installed (step 111). At last, chip performance is tested and analyzed (step 113) to determine if the performance meets the standards. The chip can be presented to the public only if the performance meets the standards; otherwise, the chip should be re-designed and/or modified.
In general, the probability of mal-functionality of a chip could be reduced with the simulation step 103. However, the fore-mentioned procedure does not guarantee that the thus produced chip has expected performance. The chip performance could be known only after the subsequent steps 109, 111, and 113. It may take a relatively long time. Moreover, if the performance fails to meet the standards after being tested, the cost as well as the efforts according to the fabrication procedure would be in vain. As a result, the thus increased cost will make the product less competitive in the market.
Therefore, there is need in providing a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing, in which the chip is produced after a simulation on design validity and product performance is carried out so as to confirm and the product advantage, such that the time requited for product testing is reduced and so is the fabrication cost.